
`define USE_YOSYS
`ifdef USE_YOSYS
(* blackbox *)
module cycloneive_clkctrl(
    ena,
	inclk,
	clkselect,
	devclrn,
	devpor,
	outclk
    );
parameter clock_type = "global clock";
parameter ena_register_mode = "none";
	input wire ena;
	input wire[3:0] inclk;
	input wire[1:0] clkselect;
	input wire devclrn;
	input wire devpor;
	output wire outclk;
endmodule

module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;
    wire devclrn;
    wire devpor;
    wire devoe;
    wire outclk;
    // Location: CLKCTRL_G2
cycloneive_clkctrl inputclkctrl (
	.ena(1'b1),
	.inclk({1'b1,1'b1,1'b1,clk_in }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(outclk ));
defparam inputclkctrl .clock_type = "global clock";
defparam inputclkctrl .ena_register_mode = "none";
    assign clk_out = outclk;
endmodule

`else
module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;
    assign clk_out = clk_in;
endmodule
`endif

(* blackbox *)
module alta_io (
  inout  padio,
  input  datain, oe,
  output combout
);
parameter coord_x = 0;
parameter coord_y = 0;
parameter coord_z = 0;
parameter PRG_DELAYB = 1'b0;
parameter RX_SEL = 1'b0;
parameter PDCNTL = 2'b11;
parameter NDCNTL = 2'b11;
parameter PRG_SLR = 1'b0;
parameter CFG_KEEP = 2'b00;
parameter PU = 4'b1000;
parameter LVDS_OUT = 1'b0;
endmodule

(* blackbox *)
module alta_clkenctrl (
  input ClkIn, ClkEn,
  output ClkOut
);
endmodule

/*定义rv32黑盒*/
(* blackbox *)
module alta_rv32 (
  input         sys_clk,
  output        mem_ahb_hready,
  input         mem_ahb_hreadyout,
  output [1:0]  mem_ahb_htrans,
  output [2:0]  mem_ahb_hsize,
  output [2:0]  mem_ahb_hburst,
  output        mem_ahb_hwrite,
  output [31:0] mem_ahb_haddr,
  output [31:0] mem_ahb_hwdata,
  input         mem_ahb_hresp,
  input  [31:0] mem_ahb_hrdata,
  input         slave_ahb_hsel,
  input         slave_ahb_hready,
  output        slave_ahb_hreadyout,
  input  [1:0]  slave_ahb_htrans,
  input  [2:0]  slave_ahb_hsize,
  input  [2:0]  slave_ahb_hburst,
  input         slave_ahb_hwrite,
  input  [31:0] slave_ahb_haddr,
  input  [31:0] slave_ahb_hwdata,
  output        slave_ahb_hresp,
  output [31:0] slave_ahb_hrdata,
  input  [7:0]  gpio0_io_in,
  output [7:0]  gpio0_io_out_data,
  output [7:0]  gpio0_io_out_en,
  input  [7:0]  gpio1_io_in,
  output [7:0]  gpio1_io_out_data,
  output [7:0]  gpio1_io_out_en,
  output [1:0]  sys_ctrl_clkSource,
  output        sys_ctrl_hseEnable,
  output        sys_ctrl_hseBypass,
  output        sys_ctrl_pllEnable,
  input         sys_ctrl_pllReady,
  output        sys_ctrl_sleep,
  output        sys_ctrl_stop,
  output        sys_ctrl_standby,
  input  [7:0]  gpio2_io_in,
  output [7:0]  gpio2_io_out_data,
  output [7:0]  gpio2_io_out_en,
  input  [7:0]  gpio3_io_in,
  output [7:0]  gpio3_io_out_data,
  output [7:0]  gpio3_io_out_en,
  input  [7:0]  gpio4_io_in,
  output [7:0]  gpio4_io_out_data,
  output [7:0]  gpio4_io_out_en,
  input  [7:0]  gpio5_io_in,
  output [7:0]  gpio5_io_out_data,
  output [7:0]  gpio5_io_out_en,
  input  [7:0]  gpio6_io_in,
  output [7:0]  gpio6_io_out_data,
  output [7:0]  gpio6_io_out_en,
  input  [7:0]  gpio7_io_in,
  output [7:0]  gpio7_io_out_data,
  output [7:0]  gpio7_io_out_en,
  input  [7:0]  gpio8_io_in,
  output [7:0]  gpio8_io_out_data,
  output [7:0]  gpio8_io_out_en,
  input  [7:0]  gpio9_io_in,
  output [7:0]  gpio9_io_out_data,
  output [7:0]  gpio9_io_out_en,
  input         ext_resetn,
  output        resetn_out,
  output        dmactive,
  output        swj_JTAGNSW,
  output [3:0]  swj_JTAGSTATE,
  output [3:0]  swj_JTAGIR,
  input  [7:0]  ext_int,
  input  [3:0]  ext_dma_DMACBREQ,
  input  [3:0]  ext_dma_DMACLBREQ,
  input  [3:0]  ext_dma_DMACSREQ,
  input  [3:0]  ext_dma_DMACLSREQ,
  output [3:0]  ext_dma_DMACCLR,
  output [3:0]  ext_dma_DMACTC,
  input  [3:0]  local_int,
  input  [1:0]  test_mode,
  input         usb0_xcvr_clk,
  input         usb0_id
);

endmodule


(* blackbox *) (* keep *)
module alta_pllve
#(parameter N=3)
(
  input  clkin, clkfb,
  input  pfden, resetn,
  input  [2:0] phasecounterselect,
  input  phaseupdown, phasestep,
  input  scanclk, scanclkena, scandata, configupdate,
  output scandataout, scandone, phasedone,
  output clkout0, clkout1, clkout2, clkout3, clkout4,
  output clkfbout, lock
);
parameter coord_x         = 0;
parameter coord_y         = 0;
parameter coord_z         = 0;
parameter CLKIN_FREQ      = "20.0";
parameter CLKIN_HIGH      = 8'b0;
parameter CLKIN_LOW       = 8'b0;
parameter CLKIN_BYPASS    = 1'b0;
parameter CLKIN_TRIM      = 1'b0;
parameter CLKFB_HIGH      = 8'd36;
parameter CLKFB_LOW       = 8'd36;
parameter CLKFB_BYPASS    = 1'b0;
parameter CLKFB_TRIM      = 1'b0;
parameter CLKDIV0_EN      = 1'b0;
parameter CLKDIV1_EN      = 1'b0;
parameter CLKDIV2_EN      = 1'b0;
parameter CLKDIV3_EN      = 1'b0;
parameter CLKDIV4_EN      = 1'b0;
parameter CLKOUT0_HIGH    = 8'b0;
parameter CLKOUT0_LOW     = 8'b0;
parameter CLKOUT0_TRIM    = 1'b0;
parameter CLKOUT0_BYPASS  = 1'b0;
parameter CLKOUT1_HIGH    = 8'b0;
parameter CLKOUT1_LOW     = 8'b0;
parameter CLKOUT1_TRIM    = 1'b0;
parameter CLKOUT1_BYPASS  = 1'b0;
parameter CLKOUT2_HIGH    = 8'b0;
parameter CLKOUT2_LOW     = 8'b0;
parameter CLKOUT2_TRIM    = 1'b0;
parameter CLKOUT2_BYPASS  = 1'b0;
parameter CLKOUT3_HIGH    = 8'b0;
parameter CLKOUT3_LOW     = 8'b0;
parameter CLKOUT3_TRIM    = 1'b0;
parameter CLKOUT3_BYPASS  = 1'b0;
parameter CLKOUT4_HIGH    = 8'b0;
parameter CLKOUT4_LOW     = 8'b0;
parameter CLKOUT4_TRIM    = 1'b0;
parameter CLKOUT4_BYPASS  = 1'b0;
parameter CLKOUT0_DEL     = 8'b0;
parameter CLKOUT1_DEL     = 8'b0;
parameter CLKOUT2_DEL     = 8'b0;
parameter CLKOUT3_DEL     = 8'b0;
parameter CLKOUT4_DEL     = 8'b0;
parameter CLKOUT0_PHASE   = 3'b0;
parameter CLKOUT1_PHASE   = 3'b0;
parameter CLKOUT2_PHASE   = 3'b0;
parameter CLKOUT3_PHASE   = 3'b0;
parameter CLKOUT4_PHASE   = 3'b0;
parameter CLKFB_DEL       = 8'b0;
parameter CLKFB_PHASE     = 3'b0;
parameter FEEDBACK_MODE   = 3'b0;
parameter FBDELAY_VAL     = 3'b0;
parameter PLLOUTP_EN      = 1'b0;
parameter PLLOUTN_EN      = 1'b0;
parameter CLKOUT1_CASCADE = 1'b0;
parameter CLKOUT2_CASCADE = 1'b0;
parameter CLKOUT3_CASCADE = 1'b0;
parameter CLKOUT4_CASCADE = 1'b0;
parameter VCO_POST_DIV    = 1'b0;
parameter REG_CTRL        = 2'b0;
parameter IVCO            = 3'b100;
parameter CP              = 3'b010;
parameter RREF            = 2'b01;
parameter RLPF            = 2'b01;
parameter RVI             = 2'b01;
parameter PLL_EN_FLAG     = 1'b0;
endmodule

(* blackbox *) (* keep *)
module alta_gclksw (
  input  resetn, ena, clkin0, clkin1, clkin2, clkin3,
  input  [1:0] select,
  output clkout
);
parameter coord_x = 0;
parameter coord_y = 0;
parameter coord_z = 0;
parameter ENA_REG_MODE = 1'b0;
endmodule

(* blackbox *) (* keep *)
module alta_rio (
  input  datain, oe, outclk, outclkena, inclk, inclkena, areset, sreset,
  output combout, regout,
  inout  padio
);
endmodule

(* blackbox *)
module alta_gclkgen (
  input  clkin, ena, mode,
  output clkout
);
endmodule

(* blackbox *)
module alta_io_gclk (
  input inclk,
  output outclk
);
endmodule


(* blackbox *)
module alta_mcu (
//inputs
    //clock and reset
    input CLK,
    input JTCK,
    input POR_n,
    input EXT_CPU_RST_n,
    input JTRST_n,
    //uart
    input UART_RXD,
    input UART_CTS_n,
    //jtag
    input JTDI,
    input JTMS,
    //ram access
    input EXT_RAM_EN,
    input EXT_RAM_WR,
    input [13:0] EXT_RAM_ADDR, //in word
    input [3:0] EXT_RAM_BYTE_EN,
    input [31:0] EXT_RAM_WDATA,
    //ext ahb slave
    input [1:0] HRESP_EXT,
    input HREADY_OUT_EXT,
    input [31:0] HRDATA_EXT,
    output [1:0] HTRANS_EXT,
    output [31:0] HADDR_EXT,
    output HWRITE_EXT,
    output HSEL_EXT,
    output [31:0] HWDATA_EXT,
    output [2:0] HSIZE_EXT,
    output HREADY_IN_EXT,
//outputs
    //flash
    output FLASH_SCK,
    output FLASH_CS_n,
    //uart
    output UART_TXD,
    output UART_RTS_n,
    //jtag
    output JTDO,
    //ram access
    output [31:0] EXT_RAM_RDATA,
//inouts
    //flash
    output FLASH_IO0_SI,
    output FLASH_IO1_SO,
    output FLASH_IO2_WPn,
    output FLASH_IO3_HOLDn,
    input  FLASH_IO0_SI_i,
    input  FLASH_IO1_SO_i,
    input  FLASH_IO2_WPn_i,
    input  FLASH_IO3_HOLDn_i,
    output FLASH_SI_OE,
    output FLASH_SO_OE,
    output WPn_IO2_OE,
    output HOLDn_IO3_OE,
    //gpio
    input [7:0]  GPIO0_I,
    input [7:0]  GPIO1_I,
    input [7:0]  GPIO2_I,
    output [7:0] GPIO0_O,
    output [7:0] GPIO1_O,
    output [7:0] GPIO2_O,
    output [7:0] nGPEN0,
    output [7:0] nGPEN1,
    output [7:0] nGPEN2
) /* synthesis syn_black_box */;
parameter coord_x = 0;
parameter coord_y = 0;
parameter coord_z = 0;
parameter [23:0] FLASH_BIAS = 24'b0;
`ifdef ALTA_SIM
M3_SYS_TOP mcu_inst(
  .CLK              (CLK              ),
  .JTCK             (JTCK             ),
  .POR_n            (POR_n            ),
  .EXT_CPU_RST_n    (EXT_CPU_RST_n    ),
  .JTRST_n          (JTRST_n          ),
  .UART_RXD         (UART_RXD         ),
  .UART_CTS_n       (UART_CTS_n       ),
  .JTDI             (JTDI             ),
  .JTMS             (JTMS             ),
  .EXT_RAM_EN       (EXT_RAM_EN       ),
  .EXT_RAM_WR       (EXT_RAM_WR       ),
  .EXT_RAM_ADDR     (EXT_RAM_ADDR     ),
  .EXT_RAM_BYTE_EN  (EXT_RAM_BYTE_EN  ),
  .EXT_RAM_WDATA    (EXT_RAM_WDATA    ),
  .FLASH_BIAS       (FLASH_BIAS       ),
  .HRESP_EXT        (HRESP_EXT        ),
  .HREADY_OUT_EXT   (HREADY_OUT_EXT   ),
  .HRDATA_EXT       (HRDATA_EXT       ),
  .HTRANS_EXT       (HTRANS_EXT       ),
  .HADDR_EXT        (HADDR_EXT        ),
  .HWRITE_EXT       (HWRITE_EXT       ),
  .HSEL_EXT         (HSEL_EXT         ),
  .HWDATA_EXT       (HWDATA_EXT       ),
  .HSIZE_EXT        (HSIZE_EXT        ),
  .HREADY_IN_EXT    (HREADY_IN_EXT    ),
  .FLASH_SCK        (FLASH_SCK        ),
  .FLASH_CS_n       (FLASH_CS_n       ),
  .UART_TXD         (UART_TXD         ),
  .UART_RTS_n       (UART_RTS_n       ),
  .JTDO             (JTDO             ),
  .EXT_RAM_RDATA    (EXT_RAM_RDATA    ),
  .FLASH_IO0_SI     (FLASH_IO0_SI     ),
  .FLASH_IO1_SO     (FLASH_IO1_SO     ),
  .FLASH_IO2_WPn    (FLASH_IO2_WPn    ),
  .FLASH_IO3_HOLDn  (FLASH_IO3_HOLDn  ),
  .FLASH_IO0_SI_i   (FLASH_IO0_SI_i   ),
  .FLASH_IO1_SO_i   (FLASH_IO1_SO_i   ),
  .FLASH_IO2_WPn_i  (FLASH_IO2_WPn_i  ),
  .FLASH_IO3_HOLDn_i(FLASH_IO3_HOLDn_i),
  .FLASH_SI_OE      (FLASH_SI_OE      ),
  .FLASH_SO_OE      (FLASH_SO_OE      ),
  .WPn_IO2_OE       (WPn_IO2_OE       ),
  .HOLDn_IO3_OE     (HOLDn_IO3_OE     ),
  .GPIO0_I          (GPIO0_I          ),
  .GPIO1_I          (GPIO1_I          ),
  .GPIO2_I          (GPIO2_I          ),
  .GPIO0_O          (GPIO0_O          ),
  .GPIO1_O          (GPIO1_O          ),
  .GPIO2_O          (GPIO2_O          ),
  .nGPEN0           (nGPEN0           ),
  .nGPEN1           (nGPEN1           ),
  .nGPEN2           (nGPEN2           )
);
`endif
endmodule


// module $_DLATCH_N_ (E, D, Q);
//   wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
//   input E, D;
//   output Q = !E ? D : Q;
// endmodule

